1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices, and more particularly to the fabrication of an elevated contact to doped regions in a CMOS device.
2) Description of the Prior Art
The semiconductor industry has been advanced in an ever brisk pace, recently. In order to achieve high performance integrated circuits or high package density of a wafer, the sizes of semiconductor devices have become smaller and smaller than before in the field of Ultra Large Scale Integrated (ULSI) technologies.
Integrated circuits includes more than millions of devices in a specific area of a wafer and electrically connecting structure for connecting these devices to perform desired function. One of the typical devices is metal oxide semiconductor field effect transistor (MOSFET). The MOSFET has been widely, traditionally applied in the semiconductor technologies. As the trend of the integrated circuits, the fabrication of the MOSFET also meets various issues to fabricate them. The typically issue that relates to hot carriers injection is overcame by the development of lightly doped drain (LDD) structure.
As transistors are scaled down even further, short channel effect (SCE) are severe. There is a challenge to make elevated source/drain (S/D) to reduce the short channel effect (SCE).
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,804,846 (Fuller) that teaches a method for a self aligned elevated S/D by W layer and chemical-mechanical polish.
U.S. Pat. No. 5,422,289 (Pierce) shows elevated source/drain (S/D) formed by chemical-mechanical polish (CMP) a poly layer.
U.S. Pat. No. 6,015,727 (Wanlass) teaches a damascene source/drain (S/D) process.
U.S. Pat. No. 5,851,883 (Gardner et al.) shows a chemical-mechanical polish (CMP) gate and S/D process.